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From verdi

This page introduces the methodology and the tools used within the Verdi project.

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UVM-SystemC methodology and library

UVM-SystemC is the Universal Verification Methodology (UVM) built in SystemC/C++, to advance current system-level verification practices. UVM-SystemC enables the creation of structured, modular, configurable and reusable testbench environment. Unlike other initiatives to create UVM in SystemC, the UVM-SystemC proof-of-concept class library uses identical constructs as defined in the UVM standard for test and sequence creation, verification component and testbench configuration and execution by means of simulation. This proof-of-concept implementation has been documented in a language reference manual, which describes all language constructs and semantics of the UVM-SystemC library. UVM-SystemC will be donated to the Accellera Systems Initiative for further industry standardization and adoption.

COSIDE design environment

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COSIDE® is the first commercial design environment based on the standards of the design language SystemC and its analog extension SystemC AMS. It allows the reliable evaluation of virtual prototypes for innovative designs. Developed by IIS/EAS, COSIDE® is the tool with which highly complex electronic or heterogeneous systems can be modeled and simulated.

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Magillem UVM Test bench generator

Magillem provides a specification driven assembly tool based on IP-XACT IEEE1685 standard allowing the generation of UVM Systemc-AMS testbenches. The tool can create the testbench architecture described by the test specification in natural language and generate the links between elements of the specification and their implementation in the testbench. The impact of change requests and modifications in the testbench are evaluated, and the traceability between test requirements, tests description, and tests implementation is ensured.

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